Hardware Master IP
Japan's first! The "Ether CAT Master IP" has been born, significantly reducing software load for high-performance SoC FPGAs.
[ Solving CPU Load and Jitter Issues in EtherCAT MASTER Communication ] To allow more users to use it flexibly, we have developed an IP for SoC FPGA. The communication engine using FPGA hardware achieves high-speed communication intervals and stable communication cycles, reducing software load. <Features> ● Automatic packet generation function ● Process communication (cyclic communication) function: 62.5μs and above ● Automatic retransmission function
- Company：エヌ・ディ・アール
- Price：Other
